Biography
Dr Wang Bo, Angela is an Assistant Professor at 亚洲色吧 and a Principal Investigator at 亚洲色吧 AI Centre since September 2020. Her research interests span various aspects of energy-efficient computing systems, architecture and circuit design, including on-device artificial intelligence, neuromorphic computing, biomedical wearables and ultra-low voltage memories. Particularly, her research work on biomedical wearables was featured by The Straits Times in 2020. She authored and co-authored many papers in prestigious journals and conferences, including JSSC, TCAS-I, TVLSI, TCAS-II, A-SSCC, MobiSys, DAC, DATE, etc. She has served as a reviewer for journals and conferences such as TCAS-I, TVLSI, TCAS-II, ICCAD and ISCAS. Since 2021, she has also served as an editorial board member of JCSC. She is a TPC member of APCCAS 2022. She was the recipient of IEEE Circuits & Systems Seoul Chapter Award in 2014.
Dr Wang received her PhD degree from Nanyang Technological University in 2015. Prior to joining 亚洲色吧, she was a research fellow, working with Professor Peh Li-Shiuan (IEEE Fellow) at the National University of Singapore from 2016 to 2020. Before that, she was a staff engineer at MediaTek Singapore. She is an IEEE senior member.
Website
About Neuromorphic Computing
Neuromorphic Computing deploys Spiking Neuron Network (SNN) models and learning rules to solve machine learning problems in a more energy-efficient way compared to conventional Artificial Neural Networks (ANN). SNN deploys all-or-nothing discrete spikes for layer-by-layer neuron communication. Similar to ANN, SNN is capable of inferencing a pre-defined problem with an analogy to biological neurons. A few ASICs, e.g. , , from industry have emerged and been showcased their superiority in power and energy efficiency as next-generation AI hardware.
Our research group is working with Professor Peh Li-Shiuan at NUS and other professors at 亚洲色吧 to design and deliver (1) energy-efficient on-chip inference and training architectures and (2) ultra-low power edge AI systems, e.g. medical wearables by leveraging SNN. For any Ph.D. applicant with interest in such a research domain, please feel free to contact Professor Wang via bo_wang@sutd.edu.sg for more information.聽Familiarity with machine learning algorithms/frameworks, RTL design with Verilog/VHDL, and/or hardware-software co-design methodology will be a strong plus.
Media Coverage
鈥淭rack Your Health with Sensor Integrated into Smartwatch? No Sweat鈥 by The Straits Times,
“A low-power, highly responsive and reusable sweat pH monitor” by NUS News,聽
“How She Got There: Women in AI and Robotics” by SGInnovate,聽
Patent
鈥淲earable Sweat Sensor鈥
- US/Europe/Japan/China Patent Application
- Singapore Non-provisional Patent Application
Selected Publications
- 鈥LAXOR: A Bit-Accurate BNN Accelerator with Latch-XOR Logic for Local Computing鈥, ACM/IEEE International Symposium on Low Power Electronics and Design, 2023 (accepted).
- 鈥淎 Digital Bit-Reconfigurable Versatile Compute-In-Memory Macro for Machine Learning Acceleration鈥, by X. Zhang, Y. Lu, B. Wang, and T. Kim, IEEE Transactions on Circuits and Systems II, 2023 (invited).
- 鈥淎 Digital Bit-Reconfigurable Versatile Compute-In-Memory Macro for Machine Learning Acceleration鈥, by X. Zhang, Y. Lu, B. Wang, and T. Kim, IEEE International Symposium on Circuits and Systems, 2023 (accepted).
- 鈥1.7pJ/SOP Neuromorphic Processor with Integrated Partial Sum Routers for In-Network Computing鈥, by B. Wang, M. M. Wong, D. Li, Y. S. Chong, J. Zhou, W. F. Wong, L. Peh, A. Mani, M. Upadhyay, A. Balaji, and A. T. Do, IEEE International Symposium on Circuits and Systems, 2023 (accepted).
- 鈥淎n 8-bit In Resistive Memory Computing Core with Regulated Passive Neuron and Bit Line Weight Mapping鈥, by Y. Zhang, K. Huang, R. Xiao, B. Wang, Y. Xu, J. Fan, and H. Shen, IEEE Transactions on Very Large Scale Integration Systems, vol. 30, no. 4, pp. 1-13, 2022.
- 鈥淩EACT: A Heterogeneous Reconfigurable Neural Network Accelerator with Software-Configurable NoCs for Training and Inference on wearables鈥, by M. Upadhyay, R. Juneja, B. Wang, J. Zhou, W. Wong, L. Peh, Design Automation Conference, pp. 1291-1296, Jul. 2022.
- 鈥淥bject-of-Interest Perception in a Reconfigurable Rolling-Crawling Robot鈥, A. Semwal, M. Lee, D. Sanchez, S. Teo, B. Wang, and R. Mohan, Sensors, vol. 22, no. 14, p. 5214, 2022.
- 鈥Modelling electrical conduction in resistive-switching-memory material via continual machine learning鈥,聽S. Go, Q. Wang, B. Wang, Y. Jiang, N. Bajalovic, D. Loke, Advanced Theory and Simulations, vol. 5, p. 2200226, 2022.
- 鈥Network-on-Chip-Centric Accelerator Architectures for Edge AI Computing鈥, B. Wang, K. Dong, N. Zakaria, M. Upadhyay, W. Wong, and L. Peh, International SoC Conference, pp. 243-244, Oct. 2022.
- 鈥淪henjing: A low power reconfigurable neuromorphic accelerator with partial-sum and spike networks-on-chip鈥, byB. Wang, J. Zhou, W. Wong and L. Peh. Design, Automation and Test in Europe Conference, Mar. 2020.
- 鈥淗yCUBE: A 0.9V 26.4 MOPS/mW, 290 pJ/cycle, Power Efficient Accelerator for IoT Applications鈥 by B. Wang, M. Karunaratne, A. Kulkarni, T. Mitra and L. Peh. IEEE Asian Solid-State Circuits Conference, Nov. 2019.
- 鈥減H Watch 鈥 Leveraging Pulse Oximeters in Existing Wearables for Reusable, Real-time Monitoring of pH in Sweat鈥 by A. Balaji, C. Yuan, B. Wang, L. Peh and H. Shao. International Conference on Mobile Systems, Applications, and Services, Jun. 2019.
- “Read bitline sensing and fast local write-back techniques in hierarchical bitline architecture for ultra-low voltage SRAMs” by B. Wang, Q. Li, and T. Kim. IEEE Transactions on Very Large Scale Integration Systems, vol 24, no. 6, 2016.
- “Design of an ultra-low voltage 9T SRAM with equalized bitline leakage and CAM-assisted energy efficiency improvement” by B. Wang, T. Q. Nguyen, A. Do, J. Zhou. M. Je, and T. Kim. IEEE Transactions on Circuits and Systems-I, vol 62, no. 2, 2015.
- “A 457-nW near-threshold cognitive multi-functional ECG processor CMOS for long-term cardiac monitoring” by X. Liu, J. Zhou, Y. Yang, B. Wang, J. Lan, C. Wang, J. Luo, W. L. Goh, T. Kim, and M. Je. IEEE Journal of Solid-State Circuits, vol 49, no. 11, 2014.
- “0.2V 8T SRAM with Improved Bitline Sensing Using Column-based Data Randomization”聽by A. Do, Z. Lee, B. Wang, I. Chang, and聽T. Kim. IEEE Asian Solid-State Circuits Conference, Nov. 2014.
- “A 0.18V charge-pumped DFF with 50.8% energy-delay reduction for near-/sub-threshold circuits” by B. Wang, J. Zhou, K. H. Chang, M. Je, and T. Kim. IEEE Asian Solid-State Circuits Conference, Nov. 2013.
- “A 457-nW Cognitive Multi-Functional ECG Processor”聽by X. Liu, J. Zhou, Y. Yang, B. Wang, J. Lan, C. Wang, J. Luo, W. L. Goh,聽T. Kim, and M. Je. IEEE Asian Solid-State Circuits Conference, Nov. 2013.
- “A 0.2V 16Kb 9T SRAM with bitline leakage equalization and CAM-assisted write performance boosting for improving energy efficiency” by B. Wang, T. Q. Nguyen, A. Do, J. Zhou. M. Je, and T. Kim. IEEE Asian Solid-State Circuits Conference, Nov. 2012.
- “A 5.61聽pJ, 16 kb 9T SRAM with Single-ended Equalized聽Bitlines聽and Fast Local Write-back for Cell Stability Improvement”聽by Q. Li, B. Wang, and聽T. Kim. IEEE European Solid-State Device Research Conference, Sep. 2012.